Design Truth
ARM platforms seem power‑efficient and easy to design, yet rising core counts and interface complexity pose severe challenges to implementing fully linear power supplies and high‑quality clocks
A common misconception is that ARM's power efficiency makes linear power supply design straightforward, while x86's higher power consumption renders it unsuitable for linear power designs.
In fact, a turning point emerged with the release of dual-core ARM processors. Some ARM manufacturers began bundling PMICs (Power Management Integrated Circuits) with their processors, with the PMIC uniformly managing all voltage rails and power-on sequencing. Here is a key concept — power-on sequencing. What is power-on sequencing? It means voltage rail A must stabilize X milliseconds before voltage rail B, and voltage rail B must stabilize Y milliseconds before voltage rail C. For example, memory operating at 1.5V must power on at least 100ms before the CPU at 0.9V, or the CPU will fail to boot because it cannot detect the memory. Since ARM systems incorporate not only memory but also external storage, ADC, DAC, and numerous functional modules — each with different power-on sequencing requirements — this management becomes extraordinarily complex. As ARM CPU core counts, interface counts, and interface types proliferate, power-on sequencing grows exponentially more intricate. Since only the original ARM manufacturers fully understand their processors' power-on sequencing requirements, they launched PMIC bundling to reduce development difficulty for their partners and increase their own revenue. The emergence of PMICs effectively solved this complexity, and using the original manufacturer's PMIC has become the de facto standard.
As ARM core counts increase and performance improves, required operating currents also grow larger. Starting from quad-core ARM, CPU power supply adopts switching power supply to address the contradiction between increased CPU power supply current and surging heat output from core count growth. Currently, industry solutions all use PMIC's built-in switching power supply to power CPU, memory and numerous circuits that significantly impact sound. Therefore, after 4 cores, ARM using PMIC almost has no possibility of being designed with full linear power supply. Of course, PMIC internally still contains a small amount of linear power supply, but these linear power supplies have minimal impact on HiFi design.
CelAudio employs the T113-S4 dual-core ARM, with the entire circuit utilizing up to 11 LDOs, completely isolating the power supply circuits for the CPU, clock, memory, external storage, I/O and network. Through our proprietary design, we achieve complete control over the T113-S4's power-on sequencing, ensuring hardware system stability — thereby realizing a stable, low-interference, fully linear power supply design for the A1 platform.
To simplify power-on sequencing design, ARM designs typically use passive crystals that can be directly controlled by the processor. As is well understood in digital audio, clock signal quality is a critical determinant of playback performance in HiFi network devices. High-quality, unified-source clocks elevate the sonic ceiling. Replacing passive crystals with high-quality, unified-source clocks is therefore the superior approach.
In the A1 architecture, CelAudio uses the CelCLK II PLL system to replace passive crystals, providing unified-source clocks for the CPU, network, and other subsystems — while overcoming the exponential increase in power-on sequencing complexity that this approach entails. The result is a native high-quality, unified-source clock system for the A1 architecture.
The CelHeart-A1 architecture is based on an ARM platform, adopting a fully linear power supply, with all clocks — including the CPU clock — unified by the CelCLK II PLL system.
The A1 architecture is a purpose-designed ARM functional module. Depending on product requirements, the A1 ARM module and specific business functions are deployed on the same circuit board, thereby meeting both functional and sonic performance requirements.
The A1 architecture employs 11 linear power management chips, with the CPU, memory, eMMC storage, network, I/O, PLL, and all other subsystems powered by linear regulators.
The T113-S4 ARM processor used in this architecture delivers performance and hardware capabilities that fully meet the demands of network bridges, routers, wireless access points, and similar applications. Combined with its automotive-grade design, it meets the most demanding environmental requirements. It is exceptionally well-suited to HiFi's fanless requirements, virtually eliminating sound quality degradation from thermal noise.
CelCLK II PLL serves as the native clock system of CelHeart A1 architecture, coexisting with A1 architecture.
CPU, network and various other clocks are all supplied by CelCLK II, and CelCLK II can receive external 10MHz clock signals, providing unlimited possibilities for A1 architecture's sound.
Since the CelHeart motherboard is platform hardware that can be deployed in various final form factors, excessive sonic coloration cannot be imposed. Beyond technical considerations, component selection is approached with great care.
No audio capacitors are used; instead, large quantities of side-effect-free SMD film capacitors are used to enhance sound liveliness and micro-dynamic performance.
Power cable locking torque can flexibly adjust sound direction. Therefore, CelHeart continues CelAudio's consistent design style since late 2022 — all power connectors use brass-tin-plated serrated screw crimp connectors, precisely calibrated by precision Tohnichi torque screwdrivers by hand, effectively adjusting the balance of sound relaxation and liveliness.